# 8 to 256 decoder

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- Subject
- Author
- Date

- 8 to 256 decoder
- Roger Bourne
- 02-23-2006

Re: 8 to 256 decoder | Spehro Pefhany | 02-23-2006

Re: 8 to 256 decoder | Tim Shoppa | 02-23-2006

Re: 8 to 256 decoder | Spehro Pefhany | 02-23-2006

Re: 8 to 256 decoder | slebetman@yahoo... | 02-23-2006

Re: 8 to 256 decoder | tlbs | 02-23-2006

Re: 8 to 256 decoder | Roger Bourne | 02-23-2006

Re: 8 to 256 decoder | Roger Bourne | 02-23-2006

Re: 8 to 256 decoder | DJ Delorie | 02-23-2006

Re: 8 to 256 decoder | Si Ballenger | 02-23-2006

Re: 8 to 256 decoder | Bob Monsen | 02-23-2006

Re: 8 to 256 decoder | Deefoo | 02-24-2006

Re: 8 to 256 decoder | Uwe Bonnes | 02-23-2006

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Posted by Roger Bourne on February 23, 2006, 9:33 am
Good day to all,
Nowadays, in 2006, what would be the best approach to make a 8 to 256
decoder?
-Regards
Roger
Posted by Spehro Pefhany on February 23, 2006, 9:55 am
On 23 Feb 2006 06:33:23 -0800, the renowned "Roger Bourne"
>Good day to all,
>Nowadays, in 2006, what would be the best approach to make a 8 to 256
>decoder?
>-Regards
>Roger
You actually want 256 outputs? Where the heck are they all going?
I think it's going to turn out to be pretty situational. If the
decoder is very slow, you could use some kind of serial SR / micro
thing. If it has to be fast and one chip, you could use programmable
BGA-packaged logic. And you could always use a whack (2^4 = 1 whack)
of 74HC154s, plus another to decode. At $3.25 USD total that one will
be hard to beat price-wise.
Posted by Tim Shoppa on February 23, 2006, 10:05 am
Roger Bourne wrote:
> Nowadays, in 2006, what would be the best approach to make a 8 to 256
> decoder?
As Spehro points out, it's hard to imagine needing all 256 decoded
outputs in one place, much less in a lot of diverse places. That's a
huge hassle to route around your PCB etc. Typically you would pipe the
8 address lines around and let whatever boards/subcircuits need some of
the decoded outputs decode only the combinations it needs. Since the
80's the preferred way of doing that decoding (tied in with enables and
clocks and whatever else is relevant) is PAL's or GAL's, today you
would probably do it with whatever programmable logic you have there
already (FPGA's, CPLD's, etc.)
The early 70's way would be 16 74154's decoding the high 4 lines, each
of these decoded outputs enabling one of 16 74154's decoding the low 4
lines.
But even in the 70's the 74154 was a bit ungainly, much more PCB-space
efficient was to use more of the smaller-packaged 74138.
Tim.
Posted by Spehro Pefhany on February 23, 2006, 10:34 am
On 23 Feb 2006 07:05:26 -0800, the renowned "Tim Shoppa"
>Roger Bourne wrote:
>> Nowadays, in 2006, what would be the best approach to make a 8 to 256
>> decoder?
>As Spehro points out, it's hard to imagine needing all 256 decoded
>outputs in one place, much less in a lot of diverse places. That's a
>huge hassle to route around your PCB etc. Typically you would pipe the
>8 address lines around and let whatever boards/subcircuits need some of
>the decoded outputs decode only the combinations it needs. Since the
>80's the preferred way of doing that decoding (tied in with enables and
>clocks and whatever else is relevant) is PAL's or GAL's, today you
>would probably do it with whatever programmable logic you have there
>already (FPGA's, CPLD's, etc.)
>The early 70's way would be 16 74154's decoding the high 4 lines, each
>of these decoded outputs enabling one of 16 74154's decoding the low 4
>lines.
>But even in the 70's the 74154 was a bit ungainly, much more PCB-space
>efficient was to use more of the smaller-packaged 74138.
>Tim.
True, however the wide SOIC-24 isn't quite as gross as the 600-mil
wide DIP-24, depending on design rules etc. TSSOP HC138s would be more
compact.
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Posted by slebetman@yahoo.com on February 23, 2006, 10:47 am
Tim Shoppa wrote:
> Roger Bourne wrote:
> > Nowadays, in 2006, what would be the best approach to make a 8 to 256
> > decoder?
> As Spehro points out, it's hard to imagine needing all 256 decoded
> outputs in one place, much less in a lot of diverse places. That's a
> huge hassle to route around your PCB etc. Typically you would pipe the
> 8 address lines around and let whatever boards/subcircuits need some of
> the decoded outputs decode only the combinations it needs. Since the
> 80's the preferred way of doing that decoding (tied in with enables and
> clocks and whatever else is relevant) is PAL's or GAL's, today you
> would probably do it with whatever programmable logic you have there
> already (FPGA's, CPLD's, etc.)
> The early 70's way would be 16 74154's decoding the high 4 lines, each
> of these decoded outputs enabling one of 16 74154's decoding the low 4
> lines.
> But even in the 70's the 74154 was a bit ungainly, much more PCB-space
> efficient was to use more of the smaller-packaged 74138.
Ah.. the venerable 74138. I remember using them to decode the bus
address on ISA cards. Still use them now to decode the address lines on
microcontroller boards though it is getting less common since most
things have gone serial (either I2C, SPI or UART).
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