# Galactic Electronics Projects

## 4 bit CPU - Memory and addressing.

The program memory is stored in 2114 static RAMs and is addressed by a program counter and a segment register. The memory address is latched during the fetch cycle and held during instruction execution. Latching the memory address is necessary because the program counter and segment register may change when the instruction is executed (during a RESTART or JUMP instructions). The new values in the program counter and segment register (if any) will be effective during the next fetch cycle.

Addressing -

The program counter is a 74LS161 four bit counter. The loading functionality of the 74LS161 is not used here, but the reset (clear) input on the 74LS161 is active low, which is desireable in this case. During program execution, the program counter is incremented for each instruction and supplies the four least significant bits of the memory address. The program counter may be reset during a reset of the CPU or by the RESTART instruction. The program counter is also reset when the segment register is changed. The AND gate on the clear input of the 74LS161 allows both the CPU reset and RESTART instruction to reset the program counter.

The segment register is a 74LS175 four bit latch. This supplies the four most significant bits of the memory address. The segment register is loaded from the accumulator during a JUMPL, JUMPE or JIMPG instruction if the appropriate flag is set.

The memory address is latched in a 74LS374 eight bit latch. The address is held in the latch during instruction execution and is updated during the fetch cycle. The outputs of the 74LS374 are tri-state and are put into high impedence mode when the memory is being loaded with a program.

Memory -

Program memory is stored in two, 2114 static RAMs. 2112s could have been used as well. Since only an eight bit address is used, a program is limited to 256 instructions. The address is supplied by the 74LS374 address latch during program run time and from the programmer interface during programming. The instruction data RAM is connected to the data bus where it can be loaded into the accumulator. The instruction code RAM is connected to the micro-instruction circutry and is used as an offset for loading the micro-instruction code. AND gates are used to generate the proper select and write signals for the 2114s. a /PRG WRITE signal from the programming interface both selects the memory and writes to it. The outputs on the 2114 are tri-state and in high impedence mode when not selected. During program run time, the program instruction RAM is always selected (read mode) while the program data RAM is selected to read only to load the accumulator with a literal value or when comparing the accumulator to a literal value.

Connections to other schematics -

Here is a listing of the connections to other schematics.

/RESET | Active low reset.
INC PC | Active high signal to increment the program counter (from EPROM).
/RESTART | Active low signal to reset the program counter (from EPROM).
LTCH SEG | Active high signal to latch the segment address into the segment register (from ALU).
LTCH INS | Active high signal to latch the program instruction into the instruction latch (from EPROM).
/E INS DATA | Active low signal to enable program data on the data bus (from EPROM).
/RUN MODE | Active low signal to enable address latch on address bus (from control / programming interface).
/PRG WRITE | Active low signal to to write to program memory (from control / programming interface).
INS0 through INS3 | Instruction code from program memory. Also connected to programming interface.
D0 through D3 | Data bus to accumulator. Also connected to programming interface.
ACC0 through ACC3 | From accumulator.
ADR0 through ADR7 | Memory address from programming interface.

Send questions and comments to WireHead@GalacticElectronics.com

(c) Jon Qualey, December 2006

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